Allwinner /D1H /UART[2] /USR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as USR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (idle)busy 0 (full)tfnf 0 (not_empty)tfe 0 (empty)rfne 0 (not_full)rff

busy=idle, tfe=not_empty, rfne=empty, rff=not_full, tfnf=full

Description

UART Status Register

Fields

busy

UART Busy Bit

0 (idle): undefined

1 (busy): undefined

tfnf

TX FIFO Not Full

0 (full): undefined

1 (not_full): undefined

tfe

TX FIFO Empty

0 (not_empty): undefined

1 (empty): undefined

rfne

RX FIFO Not Empty

0 (empty): undefined

1 (not_empty): undefined

rff

RX FIFO Full

0 (not_full): undefined

1 (full): undefined

Links

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